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ADG466/ADG467
CIRCUIT INFORMATION
Figure 17 below shows a simplified schematic of a channel
protector circuit. The circuit is made up of four MOS transis-
tors—two NMOS and two PMOS. One of the PMOS devices
does not lie directly in the signal path but is used to connect the
source of the second PMOS device to its backgate. This has the
effect of lowering the threshold voltage and so increasing the
input signal range of the channel for normal operation. The
source and backgate of the NMOS devices are connected for the
same reason. During normal operation the channel protectors
have a resistance of 60 ? typ. The channel protectors are very
low power devices, and even under fault conditions the supply
current is limited to sub microampere levels. All transistors are
dielectrically isolated from each other using a trench isolation
method. This makes it impossible to latch up the channel
protectors. For an explanation, see Trench Isolation section.
case of a negative overvoltage the threshold voltage is given by
V SS – V TP where V TP is the threshold voltage of the PMOS de-
vice (2 V typ). If the input voltage exceeds these threshold volt-
ages, the output of the channel protector (no load) is clamped at
these threshold voltages. However, the channel protector output
will clamp at a voltage that is inside these thresholds if the out-
put is loaded. For example with an output load of 1 k ? , V DD =
15 V and a positive overvoltage. The output will clamp at V DD –
V TN – ? V = 15 V – 1.5 V – 0.6 V = 12.9 V where ? V is due to I
× R voltage drop across the channels of the MOS devices (see
Figure 19). As can be seen from Figure 19, the current during
fault condition is determined by the load on the output (i.e.,
V CLAMP /R L ). However, if the supplies are off, the fault current is
limited to the nano-ampere level.
Figures 18, 20 and 21 show the operating conditions of the
signal path transistors during various fault conditions. Figure 18
shows how the channel protectors operate when a positive over-
voltage is applied to the channel protector.
V SS
V DD – V TN *
(+13.5V)
PMOS
NMOS
NMOS
POSITIVE
OVERVOLTAGE
NMOS
PMOS
NMOS
(+20V)
PMOS
SATURATED
NON-
SATURATED
NON-
SATURATED
V DD
V SS
V DD
V DD (+15V)
V SS (–15V)
V DD (+15V)
*V TN = NMOS THRESHOLD VOLTAGE (+1.5V)
Figure 17. The Channel Protector Circuit
Overvoltage Protection
When a fault condition occurs on the input of a channel protec-
tor, the voltage on the input has exceeded some threshold volt-
age set by the supply rail voltages. The threshold voltages are
related to the supply rails as follows. For a positive overvoltage,
the threshold voltage is given by V DD – V T where V TN is the
threshold voltage of the NMOS transistor (1.5 V typ). In the
Figure 18. Positive Overvoltage on the Channel Protector
The first NMOS transistor goes into a saturated mode of opera-
tion as the voltage on its Drain exceeds the Gate voltage (V DD ) –
the threshold voltage (V TN ). This situation is shown in Figure
19. The potential at the source of the NMOS device is equal to
V DD – V TN . The other MOS devices are in a nonsaturated mode of
operations.
V D
(+20V)
V G
(V DD =15V)
V S
(+13.5V)
PMOS
V
NMOS
N+
N+
OVERVOLTAGE
OPERATION
(SATURATED)
N CHANNEL
EFFECTIVE
SPACE CHARGE
REGION
(V G – V T = 13.5V)
V T = 1.5V P–
N+
NONSATURATED
OPERATION
I OUT
R L
V CLAMP
Figure 19. Positive Overvoltages Operation of the Channel Protector
REV. A
–7 –
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